Visibility Culling per Cache Block with Tiling-Traversal Algorithm

As many applications in computer graphics require render high complex 3D scenes at interactive rates, the search for an effective visibility culling method has become one of the most important issues to be addressed in the design of 3D rendering processors. In this paper, we proposed a new rasterization pipeline with visibility culling; the proposed architecture performs the visibility culling at an early stage of the rasterization pipeline by retrieving data in a pixel cache without any significant hardware logic such as hierarchical z-buffer. When the proposed visibility culling method is performed, cache block misses can occur. For reducing this occurring rate, we fetch next pixel cache blocks previously, which can be predicted by tiling-traversal algorithm. Simulation results show that the proposed architecture can achieve a performance gain of about 41% compared with the conventional pre-texturing architecture, and about 17% compare to the hierarchical z-buffer visibility scheme. Keyword: 3D graphics, graphics hardware, rendering processor, visibility culling, and pixel cache